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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:50:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 08:50:39 -0700 |
| commit | f7a9769c140f6a56e51d7384dfd8e76bf2aef66d (patch) | |
| tree | 4be49b8b30a03ac7d4deafaa7318de275d5c3a7f /passes/techmap/flowmap.cc | |
| parent | ac2aff9e28a087a9a2697cd6ccf754af738903a7 (diff) | |
| parent | a91ea6612a73568782c80bd12ce2875353e2b5c5 (diff) | |
| download | yosys-f7a9769c140f6a56e51d7384dfd8e76bf2aef66d.tar.gz yosys-f7a9769c140f6a56e51d7384dfd8e76bf2aef66d.tar.bz2 yosys-f7a9769c140f6a56e51d7384dfd8e76bf2aef66d.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'passes/techmap/flowmap.cc')
| -rw-r--r-- | passes/techmap/flowmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 0b7931e48..f5892a60e 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -397,7 +397,6 @@ struct FlowGraph pool<RTLIL::SigBit> x, xi; NodePrime source_prime = {source, true}; - NodePrime sink_prime = {sink, false}; pool<NodePrime> visited; vector<NodePrime> worklist = {source_prime}; while (!worklist.empty()) @@ -1382,7 +1381,8 @@ struct FlowmapWorker vector<RTLIL::SigBit> input_nodes(lut_edges_bw[node].begin(), lut_edges_bw[node].end()); RTLIL::Const lut_table(State::Sx, max(1 << input_nodes.size(), 1 << minlut)); - for (unsigned i = 0; i < (1 << input_nodes.size()); i++) + unsigned const mask = 1 << input_nodes.size(); + for (unsigned i = 0; i < mask; i++) { ce.push(); for (size_t n = 0; n < input_nodes.size(); n++) |