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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-19 13:04:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-08-19 13:04:06 +0200 |
| commit | 1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9 (patch) | |
| tree | 7b7830c5da434964fd40792c393c45a31b8ad080 /passes/techmap/iopadmap.cc | |
| parent | f20be90436b32e853d68c7e102a65d43f3843d91 (diff) | |
| parent | 3edb0abed88565447d5193f78261400655aa843a (diff) | |
| download | yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.tar.gz yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.tar.bz2 yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
Diffstat (limited to 'passes/techmap/iopadmap.cc')
| -rw-r--r-- | passes/techmap/iopadmap.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index efcc082d5..a2551316f 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -179,8 +179,8 @@ struct IopadmapPass : public Pass { SigMap rewrites; for (auto cell : module->cells()) - if (cell->type == "$_TBUF_") { - SigBit bit = sigmap(cell->getPort("\\Y").as_bit()); + if (cell->type == ID($_TBUF_)) { + SigBit bit = sigmap(cell->getPort(ID::Y).as_bit()); tbuf_bits[bit].first = cell->name; } @@ -212,8 +212,8 @@ struct IopadmapPass : public Pass { if (tbuf_cell == nullptr) continue; - SigBit en_sig = tbuf_cell->getPort("\\E").as_bit(); - SigBit data_sig = tbuf_cell->getPort("\\A").as_bit(); + SigBit en_sig = tbuf_cell->getPort(ID(E)).as_bit(); + SigBit data_sig = tbuf_cell->getPort(ID::A).as_bit(); if (wire->port_input && !tinoutpad_celltype.empty()) { @@ -226,7 +226,7 @@ struct IopadmapPass : public Pass { cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire); cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig); cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit); - cell->attributes["\\keep"] = RTLIL::Const(1); + cell->attributes[ID::keep] = RTLIL::Const(1); for (auto cn : tbuf_cache.second) { auto c = module->cell(cn); @@ -263,7 +263,7 @@ struct IopadmapPass : public Pass { cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig); cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig); cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit); - cell->attributes["\\keep"] = RTLIL::Const(1); + cell->attributes[ID::keep] = RTLIL::Const(1); for (auto cn : tbuf_cache.second) { auto c = module->cell(cn); @@ -390,7 +390,7 @@ struct IopadmapPass : public Pass { cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i)); - cell->attributes["\\keep"] = RTLIL::Const(1); + cell->attributes[ID::keep] = RTLIL::Const(1); } } else @@ -403,7 +403,7 @@ struct IopadmapPass : public Pass { cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); - cell->attributes["\\keep"] = RTLIL::Const(1); + cell->attributes[ID::keep] = RTLIL::Const(1); } wire->port_id = 0; |