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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
| commit | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (patch) | |
| tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/techmap/iopadmap.cc | |
| parent | cd6574ecf652901573cbc6b89e1a59dd383ec496 (diff) | |
| parent | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (diff) | |
| download | yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.gz yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.bz2 yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.zip | |
Merge automatic and manual code changes for new cell connections API
Diffstat (limited to 'passes/techmap/iopadmap.cc')
| -rw-r--r-- | passes/techmap/iopadmap.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index ba9bf51d3..114d28e25 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -177,9 +177,9 @@ struct IopadmapPass : public Pass { for (int i = 0; i < wire->width; i++) { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i); + cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i)); if (!portname2.empty()) - cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i); + cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i)); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) @@ -190,9 +190,9 @@ struct IopadmapPass : public Pass { else { RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype)); - cell->connections_[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire); + cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire)); if (!portname2.empty()) - cell->connections_[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire); + cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire)); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); if (!nameparam.empty()) |