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authorEddie Hung <eddie@fpgeh.com>2019-08-20 11:57:52 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-20 11:57:52 -0700
commitd9fe4cccbf3cc03fa57b177fd13c6e900a2134f7 (patch)
treeaceb37b755f6b112e754bbdd50f0a4a6a6ee111d /passes/techmap/lut2mux.cc
parent297a9802122817e143b1e4b87fd0d4e357606a72 (diff)
parent3f4886e7a3ff14578b9c6d614efd360478e5886e (diff)
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx
Diffstat (limited to 'passes/techmap/lut2mux.cc')
-rw-r--r--passes/techmap/lut2mux.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc
index a4ed79550..c6618fc9d 100644
--- a/passes/techmap/lut2mux.cc
+++ b/passes/techmap/lut2mux.cc
@@ -25,9 +25,9 @@ PRIVATE_NAMESPACE_BEGIN
int lut2mux(Cell *cell)
{
- SigSpec sig_a = cell->getPort("\\A");
- SigSpec sig_y = cell->getPort("\\Y");
- Const lut = cell->getParam("\\LUT");
+ SigSpec sig_a = cell->getPort(ID::A);
+ SigSpec sig_y = cell->getPort(ID::Y);
+ Const lut = cell->getParam(ID(LUT));
int count = 1;
if (GetSize(sig_a) == 1)
@@ -81,7 +81,7 @@ struct Lut2muxPass : public Pass {
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells()) {
- if (cell->type == "$lut") {
+ if (cell->type == ID($lut)) {
IdString cell_name = cell->name;
int count = lut2mux(cell);
log("Converted %s.%s to %d MUX cells.\n", log_id(module), log_id(cell_name), count);