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authorClifford Wolf <clifford@clifford.at>2019-08-19 13:04:06 +0200
committerClifford Wolf <clifford@clifford.at>2019-08-19 13:04:06 +0200
commit1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9 (patch)
tree7b7830c5da434964fd40792c393c45a31b8ad080 /passes/techmap/nlutmap.cc
parentf20be90436b32e853d68c7e102a65d43f3843d91 (diff)
parent3edb0abed88565447d5193f78261400655aa843a (diff)
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Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
Diffstat (limited to 'passes/techmap/nlutmap.cc')
-rw-r--r--passes/techmap/nlutmap.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc
index cc765d89c..798d82248 100644
--- a/passes/techmap/nlutmap.cc
+++ b/passes/techmap/nlutmap.cc
@@ -82,10 +82,10 @@ struct NlutmapWorker
for (auto cell : module->cells())
{
- if (cell->type != "$lut" || mapped_cells.count(cell))
+ if (cell->type != ID($lut) || mapped_cells.count(cell))
continue;
- if (GetSize(cell->getPort("\\A")) == lut_size || lut_size == 2)
+ if (GetSize(cell->getPort(ID::A)) == lut_size || lut_size == 2)
candidate_ratings[cell] = 0;
for (auto &conn : cell->connections())
@@ -119,7 +119,7 @@ struct NlutmapWorker
if (config.assert_mode) {
for (auto cell : module->cells())
- if (cell->type == "$lut" && !mapped_cells.count(cell))
+ if (cell->type == ID($lut) && !mapped_cells.count(cell))
log_error("Insufficient number of LUTs to map all logic cells!\n");
}