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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 16:51:22 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 16:51:22 -0700 |
commit | 24c934f1af3859fe64ff4fb87a2a3de97695cde4 (patch) | |
tree | 131c64cee5a0cf09adc68b32f25e06a9da668ad0 /passes/techmap/pmuxtree.cc | |
parent | 1c9f3fadb9f60653fc9d1d7d72ba22033e077468 (diff) | |
parent | 5abe133323b2a6a46959f796c4730b2d70cdea26 (diff) | |
download | yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.tar.gz yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.tar.bz2 yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.zip |
Merge branch 'eddie/abc9_refactor' into xaig_dff
Diffstat (limited to 'passes/techmap/pmuxtree.cc')
-rw-r--r-- | passes/techmap/pmuxtree.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc index 6a923f481..f77652f3b 100644 --- a/passes/techmap/pmuxtree.cc +++ b/passes/techmap/pmuxtree.cc @@ -89,21 +89,21 @@ struct PmuxtreePass : public Pass { for (auto module : design->selected_modules()) for (auto cell : module->selected_cells()) { - if (cell->type != "$pmux") + if (cell->type != ID($pmux)) continue; - SigSpec sig_data = cell->getPort("\\B"); - SigSpec sig_sel = cell->getPort("\\S"); + SigSpec sig_data = cell->getPort(ID(B)); + SigSpec sig_sel = cell->getPort(ID(S)); - if (!cell->getPort("\\A").is_fully_undef()) { - sig_data.append(cell->getPort("\\A")); + if (!cell->getPort(ID(A)).is_fully_undef()) { + sig_data.append(cell->getPort(ID(A))); SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel); sig_sel.append(module->Not(NEW_ID, sig_sel_or)); } SigSpec result, result_or; result = recursive_mux_generator(module, sig_data, sig_sel, result_or); - module->connect(cell->getPort("\\Y"), result); + module->connect(cell->getPort(ID(Y)), result); module->remove(cell); } } |