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authorDavid Shah <dave@ds0.me>2019-08-30 13:57:15 +0100
committerDavid Shah <dave@ds0.me>2019-08-30 13:57:15 +0100
commit6919c0f9b010c94a0a1a31cd788301e78a1bcbfb (patch)
tree4780799b6c1dc1d150b80aa142e6c53e06760cb3 /passes/techmap/pmuxtree.cc
parentedff79a25a802e5b1816608b48e3ac335ad87147 (diff)
parent694e30a35426b9582a1f2db730528d4d34305795 (diff)
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Merge branch 'master' into xc7dsp
Diffstat (limited to 'passes/techmap/pmuxtree.cc')
-rw-r--r--passes/techmap/pmuxtree.cc12
1 files changed, 6 insertions, 6 deletions
diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc
index 6a923f481..31ab13cec 100644
--- a/passes/techmap/pmuxtree.cc
+++ b/passes/techmap/pmuxtree.cc
@@ -89,21 +89,21 @@ struct PmuxtreePass : public Pass {
for (auto module : design->selected_modules())
for (auto cell : module->selected_cells())
{
- if (cell->type != "$pmux")
+ if (cell->type != ID($pmux))
continue;
- SigSpec sig_data = cell->getPort("\\B");
- SigSpec sig_sel = cell->getPort("\\S");
+ SigSpec sig_data = cell->getPort(ID::B);
+ SigSpec sig_sel = cell->getPort(ID(S));
- if (!cell->getPort("\\A").is_fully_undef()) {
- sig_data.append(cell->getPort("\\A"));
+ if (!cell->getPort(ID::A).is_fully_undef()) {
+ sig_data.append(cell->getPort(ID::A));
SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel);
sig_sel.append(module->Not(NEW_ID, sig_sel_or));
}
SigSpec result, result_or;
result = recursive_mux_generator(module, sig_data, sig_sel, result_or);
- module->connect(cell->getPort("\\Y"), result);
+ module->connect(cell->getPort(ID::Y), result);
module->remove(cell);
}
}