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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 18:09:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 18:09:38 -0700 |
| commit | 31ff0d8ef529a1ddfa37e4b68017e4e433399da7 (patch) | |
| tree | 921a3a801a4e7bc9d8998b0aa7f21506db7881e6 /passes/techmap/shregmap.cc | |
| parent | e97178a888cebc6acacb8f8f2c68d4f9743a9284 (diff) | |
| parent | f86d153cef724af9d30e4139783a7e14d7ba0a19 (diff) | |
| download | yosys-31ff0d8ef529a1ddfa37e4b68017e4e433399da7.tar.gz yosys-31ff0d8ef529a1ddfa37e4b68017e4e433399da7.tar.bz2 yosys-31ff0d8ef529a1ddfa37e4b68017e4e433399da7.zip | |
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
Diffstat (limited to 'passes/techmap/shregmap.cc')
| -rw-r--r-- | passes/techmap/shregmap.cc | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index a541b33be..75eedfbcc 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -178,7 +178,17 @@ struct ShregmapTechXilinx7 : ShregmapTech // Only map if $shiftx exclusively covers the shift register if (shiftx->type == "$shiftx") { - if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) + if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int()) + return false; + // Due to padding the most significant bits of A may be 1'bx, + // and if so, discount them + if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) { + const SigSpec A = shiftx->getPort("\\A"); + const int A_width = shiftx->getParam("\\A_WIDTH").as_int(); + for (int i = GetSize(taps); i < A_width; ++i) + if (A[i] != RTLIL::Sx) return false; + } + else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int()) return false; } else if (shiftx->type == "$mux") { |