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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 17:03:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-22 16:16:56 -0700 |
| commit | 53fed4f7e9cd6512762cf93c74464d8e40efb414 (patch) | |
| tree | d6f1a8686d01e46b8e36fb56cfac674a85f27a7f /passes/techmap/shregmap.cc | |
| parent | cfafd360d52795c9c76c69d008f765d171e2b0ed (diff) | |
| download | yosys-53fed4f7e9cd6512762cf93c74464d8e40efb414.tar.gz yosys-53fed4f7e9cd6512762cf93c74464d8e40efb414.tar.bz2 yosys-53fed4f7e9cd6512762cf93c74464d8e40efb414.zip | |
Actually, there might not be any harm in updating sigmap...
Diffstat (limited to 'passes/techmap/shregmap.cc')
| -rw-r--r-- | passes/techmap/shregmap.cc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index f308292fa..9da69e8ba 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -151,11 +151,9 @@ struct ShregmapWorker // so that it can be identified as another chain // (omitting this common flop) // Link: https://github.com/YosysHQ/yosys/pull/1085 - // NB: This relies on us not updating sigmap with this - // alias otherwise it would think they are the same - // wire Wire *wire = module->addWire(NEW_ID); module->connect(wire, d_bit); + sigmap.add(wire, d_bit); sigbit_chain_next.insert(std::make_pair(wire, cell)); } |