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| author | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-14 12:06:57 +0200 |
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| committer | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-14 12:06:57 +0200 |
| commit | fe651922cbc4ab086354c04652adc986b31305fd (patch) | |
| tree | e06a152dbc08ffac344c1a9139b0c43b0651239f /passes/techmap/shregmap.cc | |
| parent | 53695e6729e8ae603be7e7cd9bc8b29758d61a11 (diff) | |
| parent | d4f77d408c754285969969bda3a6985c1fbe9fb6 (diff) | |
| download | yosys-fe651922cbc4ab086354c04652adc986b31305fd.tar.gz yosys-fe651922cbc4ab086354c04652adc986b31305fd.tar.bz2 yosys-fe651922cbc4ab086354c04652adc986b31305fd.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'passes/techmap/shregmap.cc')
| -rw-r--r-- | passes/techmap/shregmap.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 75eedfbcc..21dfe9619 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -606,6 +606,9 @@ struct ShregmapPass : public Pass { log(" -tech greenpak4\n"); log(" map to greenpak4 shift registers.\n"); log("\n"); + log(" -tech xilinx\n"); + log(" map to xilinx dynamic-length shift registers.\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { |