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authorClifford Wolf <clifford@clifford.at>2017-09-01 12:33:47 +0200
committerClifford Wolf <clifford@clifford.at>2017-09-01 12:33:47 +0200
commit307dc55d65f9b9c07c10f6043ce0f165aac3852e (patch)
tree3c48790ce444bc2de95d20b01181f6d871e53fbb /passes/techmap/techmap.cc
parent85303334396904edfa0d77852b77c64870468f79 (diff)
parent8a66bd30c67c753149a195b951a3191d8e5e3304 (diff)
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Merge branch 'ChipScan-master'
Diffstat (limited to 'passes/techmap/techmap.cc')
-rw-r--r--passes/techmap/techmap.cc5
1 files changed, 5 insertions, 0 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index ae89453d0..d9e81e808 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -340,6 +340,8 @@ struct TechmapWorker
RTLIL::Cell *c = module->addCell(c_name, it.second);
design->select(module, c);
+ c->set_src_attribute(cell->get_src_attribute());
+
if (!flatten_mode && c->type.substr(0, 2) == "\\$")
c->type = c->type.substr(1);
@@ -465,6 +467,7 @@ struct TechmapWorker
bool mapped_cell = false;
std::string cell_type = cell->type.str();
+
if (in_recursion && cell_type.substr(0, 2) == "\\$")
cell_type = cell_type.substr(1);
@@ -512,6 +515,8 @@ struct TechmapWorker
extmapper_module = extmapper_design->addModule(m_name);
RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
+ extmapper_cell->set_src_attribute(cell->get_src_attribute());
+
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));