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| author | Clifford Wolf <clifford@clifford.at> | 2019-09-05 13:51:53 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-09-05 13:51:53 +0200 |
| commit | 30f1ac7ce9c44ac5cbd4ad7e389264246a1e3306 (patch) | |
| tree | 98a5d666279a6a767472b63e50edf450ed410ff7 /passes/techmap/techmap.cc | |
| parent | 694a8f75cf7a8bcf86a421ca6c9fe3560b1e2a0f (diff) | |
| download | yosys-30f1ac7ce9c44ac5cbd4ad7e389264246a1e3306.tar.gz yosys-30f1ac7ce9c44ac5cbd4ad7e389264246a1e3306.tar.bz2 yosys-30f1ac7ce9c44ac5cbd4ad7e389264246a1e3306.zip | |
Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/techmap/techmap.cc')
| -rw-r--r-- | passes/techmap/techmap.cc | 32 |
1 files changed, 24 insertions, 8 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index cb01cadb1..5ce1bf7d6 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -205,6 +205,7 @@ struct TechmapWorker } std::map<RTLIL::IdString, RTLIL::IdString> positional_ports; + dict<Wire*, IdString> temp_renamed_wires; for (auto &it : tpl->wires_) { if (it.second->port_id > 0) @@ -213,15 +214,20 @@ struct TechmapWorker apply_prefix(cell->name, w_name); RTLIL::Wire *w = module->wire(w_name); if (w != nullptr) { - if (!flatten_mode) - log_error("Signal %s.%s conflicts with %s.%s (via %s.%s).\n", log_id(module), log_id(w), - log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); - if (GetSize(w) < GetSize(it.second)) { - log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w), - log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); - w->width = GetSize(it.second); + if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) { + temp_renamed_wires[w] = w->name; + module->rename(w, NEW_ID); + w = nullptr; + } else { + w->attributes.erase(ID(hierconn)); + if (GetSize(w) < GetSize(it.second)) { + log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w), + log_id(tpl), log_id(it.second), log_id(module), log_id(cell)); + w->width = GetSize(it.second); + } } - } else { + } + if (w == nullptr) { w = module->addWire(w_name, it.second); w->port_input = false; w->port_output = false; @@ -392,6 +398,16 @@ struct TechmapWorker } module->remove(cell); + + for (auto &it : temp_renamed_wires) + { + Wire *w = it.first; + IdString name = it.second; + IdString altname = module->uniquify(name); + Wire *other_w = module->wire(name); + module->rename(other_w, altname); + module->rename(w, name); + } } bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells, |