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author | whitequark <whitequark@whitequark.org> | 2020-08-27 11:24:06 +0000 |
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committer | GitHub <noreply@github.com> | 2020-08-27 11:24:06 +0000 |
commit | 702f7c0253dcf9410050586a5e56da044e3277a3 (patch) | |
tree | ab94c9121ceb78152a538843e82f69228e938dde /passes/techmap/techmap.cc | |
parent | 880df4c89763464b471b1e2044f3f296bb3332b4 (diff) | |
parent | 00e7dec7f54eb2e4f18112e5c0007a55287fdf8e (diff) | |
download | yosys-702f7c0253dcf9410050586a5e56da044e3277a3.tar.gz yosys-702f7c0253dcf9410050586a5e56da044e3277a3.tar.bz2 yosys-702f7c0253dcf9410050586a5e56da044e3277a3.zip |
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil
Replace "ILANG" with "RTLIL" everywhere
Diffstat (limited to 'passes/techmap/techmap.cc')
-rw-r--r-- | passes/techmap/techmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 4a1a74ce9..5cd35929e 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -985,7 +985,7 @@ struct TechmapPass : public Pass { log(" techmap [-map filename] [selection]\n"); log("\n"); log("This pass implements a very simple technology mapper that replaces cells in\n"); - log("the design with implementations given in form of a Verilog or ilang source\n"); + log("the design with implementations given in form of a Verilog or RTLIL source\n"); log("file.\n"); log("\n"); log(" -map filename\n"); @@ -1212,7 +1212,7 @@ struct TechmapPass : public Pass { if (!map->module(mod->name)) map->add(mod->clone()); } else { - Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend)); + Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend)); } } |