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authorClifford Wolf <clifford@clifford.at>2013-03-18 07:33:53 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-18 07:33:53 +0100
commitbc5489f7ec22628553c587df3bcf40cea47cf755 (patch)
tree161eb60f3165149eef22ce57024338c022a3f9b7 /passes/techmap/techmap.cc
parentba3793b6420f2a0288c43be0cd4016fd5473acaf (diff)
parent020a35d11e26e5487ae3568ac78df28c14019375 (diff)
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Merge branch 'hansi'
Diffstat (limited to 'passes/techmap/techmap.cc')
-rw-r--r--passes/techmap/techmap.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index c05a96cd4..5fd5858aa 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -172,14 +172,14 @@ struct TechmapPass : public Pass {
log("\n");
log(" techmap [-map filename] [selection]\n");
log("\n");
- log("This pass implements a very simple technology mapper than replaces cells in\n");
+ log("This pass implements a very simple technology mapper that replaces cells in\n");
log("the design with implementations given in form of a verilog or ilang source\n");
log("file.\n");
log("\n");
log(" -map filename\n");
log(" the library of cell implementations to be used.\n");
log(" without this parameter a builtin library is used that\n");
- log(" transform the internal RTL cells to the internal gate\n");
+ log(" transforms the internal RTL cells to the internal gate\n");
log(" library.\n");
log("\n");
log("See 'help extract' for a pass that does the opposite thing.\n");