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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 11:47:25 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-02 11:47:25 -0700 |
| commit | 5f662b1c43052bf48558be12ff0013f2e39ae9ab (patch) | |
| tree | 2e0bb8da3b23cc1bfac332115502759223afea52 /passes/techmap/zinit.cc | |
| parent | 0ed1062557ac9c7fd3d930ffc75f6df9424a87cd (diff) | |
| parent | 956ecd48f71417b514c194a833a49238049e00b0 (diff) | |
| download | yosys-5f662b1c43052bf48558be12ff0013f2e39ae9ab.tar.gz yosys-5f662b1c43052bf48558be12ff0013f2e39ae9ab.tar.bz2 yosys-5f662b1c43052bf48558be12ff0013f2e39ae9ab.zip | |
Merge pull request #1767 from YosysHQ/eddie/idstrings
IdString: use more ID::*, make them easier to use, speed up IdString::in()
Diffstat (limited to 'passes/techmap/zinit.cc')
| -rw-r--r-- | passes/techmap/zinit.cc | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc index ac3d4ed4a..a427c4987 100644 --- a/passes/techmap/zinit.cc +++ b/passes/techmap/zinit.cc @@ -62,12 +62,12 @@ struct ZinitPass : public Pass { for (auto wire : module->selected_wires()) { - if (wire->attributes.count(ID(init)) == 0) + if (wire->attributes.count(ID::init) == 0) continue; SigSpec wirebits = sigmap(wire); - Const initval = wire->attributes.at(ID(init)); - wire->attributes.erase(ID(init)); + Const initval = wire->attributes.at(ID::init); + wire->attributes.erase(ID::init); for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) { @@ -103,8 +103,8 @@ struct ZinitPass : public Pass { if (!dff_types.count(cell->type)) continue; - SigSpec sig_d = sigmap(cell->getPort(ID(D))); - SigSpec sig_q = sigmap(cell->getPort(ID(Q))); + SigSpec sig_d = sigmap(cell->getPort(ID::D)); + SigSpec sig_q = sigmap(cell->getPort(ID::Q)); if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1) continue; @@ -120,14 +120,14 @@ struct ZinitPass : public Pass { } Wire *initwire = module->addWire(NEW_ID, GetSize(initval)); - initwire->attributes[ID(init)] = initval; + initwire->attributes[ID::init] = initval; for (int i = 0; i < GetSize(initwire); i++) if (initval.bits.at(i) == State::S1) { sig_d[i] = module->NotGate(NEW_ID, sig_d[i]); module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]); - initwire->attributes[ID(init)].bits.at(i) = State::S0; + initwire->attributes[ID::init].bits.at(i) = State::S0; } else { @@ -137,8 +137,8 @@ struct ZinitPass : public Pass { log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type), log_signal(sig_q), log_signal(initval)); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), initwire); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, initwire); } for (auto &it : initbits) |