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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 16:40:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 16:40:53 -0700 |
| commit | 00c5ceb1f2c28435fa245a5183d325c441b8e5eb (patch) | |
| tree | 7da553846321ce8c1371635469aa9d2a2039b3bd /passes/techmap | |
| parent | 1826370b3ab1485f966a796b95860779ae1dbd69 (diff) | |
| download | yosys-00c5ceb1f2c28435fa245a5183d325c441b8e5eb.tar.gz yosys-00c5ceb1f2c28435fa245a5183d325c441b8e5eb.tar.bz2 yosys-00c5ceb1f2c28435fa245a5183d325c441b8e5eb.zip | |
abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 8d55b18a0..16b468b19 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -719,8 +719,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff) bit_users[bit].insert(cell->name); if (cell->output(conn.first) && !abc9_flop) - for (auto bit : sigmap(conn.second)) - bit_drivers[bit].insert(cell->name); + for (const auto &chunk : conn.second.chunks()) + if (!chunk.wire->get_bool_attribute(ID::abc9_keep)) + for (auto b : sigmap(SigSpec(chunk))) + bit_drivers[b].insert(cell->name); } toposort.node(cell->name); } |