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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 00:29:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:57 -0700 |
| commit | 13f9d65b6fc09af76330c02ab420324b50db61da (patch) | |
| tree | c2e403d93adf7e029feb4c489ac45cb6ac89d634 /passes/techmap | |
| parent | fa31e84112c004348fae30e64ca224367b71d187 (diff) | |
| download | yosys-13f9d65b6fc09af76330c02ab420324b50db61da.tar.gz yosys-13f9d65b6fc09af76330c02ab420324b50db61da.tar.bz2 yosys-13f9d65b6fc09af76330c02ab420324b50db61da.zip | |
abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 18 |
1 files changed, 1 insertions, 17 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 41a11e9a7..03a3c5583 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -1101,17 +1101,6 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) map_autoidx = autoidx++; - // TODO: Get rid of this expensive lookup - dict<SigBit,vector<SigBit>> sig2inits; - SigMap sigmap(module); - for (auto w : module->wires()) { - auto it = w->attributes.find(ID::init); - if (it == w->attributes.end()) - continue; - for (const auto &b : SigSpec(w)) - sig2inits[sigmap(b)].emplace_back(b); - } - RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str())); if (mapped_mod == NULL) log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module)); @@ -1164,12 +1153,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode) // Short out $_DFF_[NP]_ cells since the flop box already has // all the information we need to reconstruct cell if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) { - SigBit Q = cell->getPort(ID::Q); - auto it = sig2inits.find(Q); - if (it != sig2inits.end()) - for (const auto &b : it->second) - b.wire->attributes.at(ID::init)[b.offset] = State::Sx; - module->connect(Q, cell->getPort(ID::D)); + module->connect(cell->getPort(ID::Q), cell->getPort(ID::D)); module->remove(cell); } else if (cell->type.in(ID($_AND_), ID($_NOT_))) |