diff options
author | gatecat <gatecat@ds0.me> | 2022-05-01 09:24:17 +0100 |
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committer | Lofty <dan.ravensloft@gmail.com> | 2022-05-23 15:02:25 +0100 |
commit | 166a175983edeacb9494e084ef84f6f7fdec1d91 (patch) | |
tree | a1c8952af80ca4df38fcc8523784dd1c3f158f18 /passes/techmap | |
parent | 0b1a1a576bda094702d1233a48ade16caf96b8f4 (diff) | |
download | yosys-166a175983edeacb9494e084ef84f6f7fdec1d91.tar.gz yosys-166a175983edeacb9494e084ef84f6f7fdec1d91.tar.bz2 yosys-166a175983edeacb9494e084ef84f6f7fdec1d91.zip |
abc9_ops: Don't leave unused derived modules lying around
These later become accidentally used for techmap replacements for
blackboxes that we don't actually want.
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'passes/techmap')
-rw-r--r-- | passes/techmap/abc9_ops.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index b8975f178..acafb0b65 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -155,6 +155,9 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) r.first->second = new Design; Design *unmap_design = r.first->second; + // Keep track of derived versions of modules that we haven't used, to prevent these being used for unwanted techmaps later on. + pool<IdString> unused_derived; + for (auto module : design->selected_modules()) for (auto cell : module->cells()) { auto inst_module = design->module(cell->type); @@ -169,6 +172,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) else { derived_type = inst_module->derive(design, cell->parameters); derived_module = design->module(derived_type); + unused_derived.insert(derived_type); } if (derived_module->get_bool_attribute(ID::abc9_flop)) { @@ -192,6 +196,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) // as a compatible type, yet will be safely unmapped later cell->type = derived_type; cell->parameters.clear(); + unused_derived.erase(derived_type); } continue; } @@ -250,7 +255,11 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) cell->type = derived_type; cell->parameters.clear(); + unused_derived.erase(derived_type); } + for (auto unused : unused_derived) { + design->remove(design->module(unused)); + } } void prep_bypass(RTLIL::Design *design) |