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| author | whitequark <whitequark@whitequark.org> | 2021-01-26 18:29:16 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2021-01-26 18:29:53 +0000 |
| commit | 2364820f504beef06d0d94d6b2e82eddffeb57c1 (patch) | |
| tree | d6d655c4c2d254155adffb3eab1c616def5162f0 /passes/techmap | |
| parent | 8eaeaa8434681403d12ac5d6a9761d3720b4ef98 (diff) | |
| download | yosys-2364820f504beef06d0d94d6b2e82eddffeb57c1.tar.gz yosys-2364820f504beef06d0d94d6b2e82eddffeb57c1.tar.bz2 yosys-2364820f504beef06d0d94d6b2e82eddffeb57c1.zip | |
flatten: clarify confusing error message.
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/flatten.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index ec5f83fb0..f35b7ff60 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -211,7 +211,7 @@ struct FlattenWorker log_assert(new_conn.first.size() == new_conn.second.size()); if (sigmap(new_conn.first).has_const()) - log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n", + log_error("Cell port %s.%s.%s is driving constant bits: %s <= %s\n", log_id(module), log_id(cell), log_id(port_it.first), log_signal(new_conn.first), log_signal(new_conn.second)); module->connect(new_conn); |