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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:22:37 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 13:22:37 -0700 |
| commit | 3c1c376fb126017b8c3fdc3811830da11a15b635 (patch) | |
| tree | c6bed947017c216f1a3670f23183574b5d595a2c /passes/techmap | |
| parent | 455da572723e4f19ddc1d636b700a5fe1e975fbb (diff) | |
| download | yosys-3c1c376fb126017b8c3fdc3811830da11a15b635.tar.gz yosys-3c1c376fb126017b8c3fdc3811830da11a15b635.tar.bz2 yosys-3c1c376fb126017b8c3fdc3811830da11a15b635.zip | |
Revert to upstream
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 919c4ce53..0a5b07e6f 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1194,7 +1194,8 @@ struct Abc9Pass : public Pass { std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down; std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down; - for (auto cell : all_cells) { + for (auto cell : all_cells) + { clkdomain_t key; for (auto &conn : cell->connections()) @@ -1228,7 +1229,6 @@ struct Abc9Pass : public Pass { else continue; - unassigned_cells.erase(cell); expand_queue.insert(cell); expand_queue_up.insert(cell); |