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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-04-08 17:38:54 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-04-08 17:38:54 +0200 |
| commit | 4772bc70d016f326da935441f75cd9b80329b681 (patch) | |
| tree | b40a8efa6fcd16622f7569c1fb04f0f2b9c7b098 /passes/techmap | |
| parent | bd7ee79486d4e8788f36de8c25a3fb2df451d682 (diff) | |
| parent | 868409361c4b5b3c4382281a289fd38abc196e63 (diff) | |
| download | yosys-4772bc70d016f326da935441f75cd9b80329b681.tar.gz yosys-4772bc70d016f326da935441f75cd9b80329b681.tar.bz2 yosys-4772bc70d016f326da935441f75cd9b80329b681.zip | |
Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix
Use wrap_async_control_gate if ff is fine
Diffstat (limited to 'passes/techmap')
0 files changed, 0 insertions, 0 deletions