Fixed all users of SigSpec::chunks_rw() and removed it

3 files changed, 24 insertions, 25 deletions

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 1687a1ffb..e5055c9c4 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -755,11 +755,11 @@ struct ExtractPass : public Pass {
 					newCell->type = cell->type;
 					newCell->parameters = cell->parameters;
 					for (auto &conn : cell->connections) {
-						RTLIL::SigSpec sig = sigmap(conn.second);
-						for (auto &chunk : sig.chunks_rw())
+						std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
+						for (auto &chunk : chunks)
 							if (chunk.wire != NULL)
 								chunk.wire = newMod->wires.at(chunk.wire->name);
-						newCell->connections[conn.first] = sig;
+						newCell->connections[conn.first] = chunks;
 					}
 					newMod->add(newCell);
 				}
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index 53c5d1044..51b8802c4 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -26,36 +26,34 @@ static std::string locell_celltype, locell_portname;
 static bool singleton_mode;
 
 static RTLIL::Module *module;
-static RTLIL::SigChunk last_hi, last_lo;
+static RTLIL::SigBit last_hi, last_lo;
 
 void hilomap_worker(RTLIL::SigSpec &sig)
 {
-	sig.expand();
-	for (auto &c : sig.chunks_rw()) {
-		if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
-			if (!singleton_mode || last_hi.width == 0) {
-				last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));
+	for (auto &bit : sig) {
+		if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
+			if (!singleton_mode || last_hi == RTLIL::State::Sm) {
+				last_hi = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = new RTLIL::Cell;
 				cell->name = NEW_ID;
 				cell->type = RTLIL::escape_id(hicell_celltype);
 				cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi;
 				module->add(cell);
 			}
-			c = last_hi;
+			bit = last_hi;
 		}
-		if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S0) && !locell_celltype.empty()) {
-			if (!singleton_mode || last_lo.width == 0) {
-				last_lo = RTLIL::SigChunk(module->addWire(NEW_ID));
+		if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
+			if (!singleton_mode || last_lo == RTLIL::State::Sm) {
+				last_lo = module->addWire(NEW_ID);
 				RTLIL::Cell *cell = new RTLIL::Cell;
 				cell->name = NEW_ID;
 				cell->type = RTLIL::escape_id(locell_celltype);
 				cell->connections[RTLIL::escape_id(locell_portname)] = last_lo;
 				module->add(cell);
 			}
-			c = last_lo;
+			bit = last_lo;
 		}
 	}
-	sig.optimize();
 }
 
 struct HilomapPass : public Pass {
@@ -119,8 +117,8 @@ struct HilomapPass : public Pass {
 			if (!design->selected(module))
 				continue;
 
-			last_hi = RTLIL::SigChunk();
-			last_lo = RTLIL::SigChunk();
+			last_hi = RTLIL::State::Sm;
+			last_lo = RTLIL::State::Sm;
 
 			module->rewrite_sigspecs(hilomap_worker);
 		}
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index f3b1a0ef7..8d7b21e0f 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -41,14 +41,15 @@ static void apply_prefix(std::string prefix, std::string &id)
 
 static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
 {
-	for (size_t i = 0; i < sig.chunks().size(); i++) {
-		if (sig.chunks()[i].wire == NULL)
-			continue;
-		std::string wire_name = sig.chunks()[i].wire->name;
-		apply_prefix(prefix, wire_name);
-		assert(module->wires.count(wire_name) > 0);
-		sig.chunks_rw()[i].wire = module->wires[wire_name];
-	}
+	std::vector<RTLIL::SigChunk> chunks = sig;
+	for (auto &chunk : chunks)
+		if (chunk.wire != NULL) {
+			std::string wire_name = chunk.wire->name;
+			apply_prefix(prefix, wire_name);
+			assert(module->wires.count(wire_name) > 0);
+			chunk.wire = module->wires[wire_name];
+		}
+	sig = chunks;
 }
 
 struct TechmapWorker