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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-21 21:39:13 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-21 21:39:13 -0700 |
| commit | 4f0f32116956782059d415a13ac52bf056634d6f (patch) | |
| tree | a36f88f5d787454a8da2aae6c255dc497748f4fc /passes/techmap | |
| parent | 574812d9a54881784b104c71ba56a2e6ed14d39f (diff) | |
| download | yosys-4f0f32116956782059d415a13ac52bf056634d6f.tar.gz yosys-4f0f32116956782059d415a13ac52bf056634d6f.tar.bz2 yosys-4f0f32116956782059d415a13ac52bf056634d6f.zip | |
abc9_ops: update comment
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 10c980f73..8d55b18a0 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -547,7 +547,7 @@ void mark_scc(RTLIL::Module *module) // For every unique SCC found, (arbitrarily) find the first // cell in the component, and replace its output connections // with a new wire driven by the old connection but with a - // special (* abc9_scc *) attribute set (which is used by + // special (* abc9_keep *) attribute set (which is used by // write_xaiger to break this wire into PI and POs) pool<RTLIL::Const> ids_seen; for (auto cell : module->cells()) { |