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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 10:05:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 10:05:42 +0200 |
| commit | 5b51b67297a5e5e20cbe2b015b584aee4c30489f (patch) | |
| tree | 934ce8ee55c3c58a1e2c11f19eec194665413906 /passes/techmap | |
| parent | c61467a32c4bd3ec4b9e0cb6d36d602f0e4dea81 (diff) | |
| parent | ec923652e2eb721aa16657e54a67666f855c3d65 (diff) | |
| download | yosys-5b51b67297a5e5e20cbe2b015b584aee4c30489f.tar.gz yosys-5b51b67297a5e5e20cbe2b015b584aee4c30489f.tar.bz2 yosys-5b51b67297a5e5e20cbe2b015b584aee4c30489f.zip | |
Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/extract.cc | 2 | ||||
| -rw-r--r-- | passes/techmap/iopadmap.cc | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 5a7298087..1687a1ffb 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -315,7 +315,7 @@ namespace RTLIL::Wire *wire = it.second; if (wire->port_id > 0) { for (int i = 0; i < wire->width; i++) - sig2port.insert(sigmap(RTLIL::SigSpec(wire, 1, i)), std::pair<std::string, int>(wire->name, i)); + sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i)); cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width); } } diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index eb2757f66..09147383a 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -179,9 +179,9 @@ struct IopadmapPass : public Pass { RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = RTLIL::escape_id(celltype); - cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, 1, i); + cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i); if (!portname2.empty()) - cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, 1, i); + cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i); if (!widthparam.empty()) cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1); if (!nameparam.empty()) |