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author | Clifford Wolf <clifford@clifford.at> | 2013-11-23 16:49:58 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-11-23 16:49:58 +0100 |
commit | 5f9c7fc6eadd7bc70e13df4131c059ec9ae18103 (patch) | |
tree | f535b084aee342eb21dcfc1f9a6bed16ce87db6b /passes/techmap | |
parent | 1de12e1efc9d346d4c1847ddf9a85c38e9b503ee (diff) | |
download | yosys-5f9c7fc6eadd7bc70e13df4131c059ec9ae18103.tar.gz yosys-5f9c7fc6eadd7bc70e13df4131c059ec9ae18103.tar.bz2 yosys-5f9c7fc6eadd7bc70e13df4131c059ec9ae18103.zip |
Improved handling of techmap special wires
Diffstat (limited to 'passes/techmap')
-rw-r--r-- | passes/techmap/techmap.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 0bc19c348..e273769d1 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -78,7 +78,7 @@ static TechmapWires techmap_find_special_wires(RTLIL::Module *module) record.value = it.second; result[p].push_back(record); it.second->attributes["\\keep"] = RTLIL::Const(1); - it.second->attributes["\\_techmap_attr_"] = RTLIL::Const(1); + it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1); } } @@ -112,6 +112,8 @@ static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, w->port_input = false; w->port_output = false; w->port_id = 0; + if (it.second->get_bool_attribute("\\_techmap_special_")) + w->attributes.clear(); module->wires[w->name] = w; design->select(module, w); } |