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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-18 08:41:48 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 9dcf204dece518a48192a90ea962a9d630283e11 (patch) | |
| tree | 0903d1fda546051d2c2e8ac7f8af41334ca5d7a4 /passes/techmap | |
| parent | 7c3b4b80ea62c53e3f4bd6d91dcf02ef09c40da7 (diff) | |
| download | yosys-9dcf204dece518a48192a90ea962a9d630283e11.tar.gz yosys-9dcf204dece518a48192a90ea962a9d630283e11.tar.bz2 yosys-9dcf204dece518a48192a90ea962a9d630283e11.zip | |
TimingInfo: index by (port_name,offset)
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index f7097fadb..e5de2bcc4 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -473,11 +473,11 @@ void prep_lut(RTLIL::Design *design, int maxlut) auto &t = timing.setup_module(module); - SigBit o; + TimingInfo::NameBit o; std::vector<int> specify; for (const auto &i : t.comb) { auto &d = i.first.second; - if (o == SigBit()) + if (o == TimingInfo::NameBit()) o = d; else if (o != d) log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module)); @@ -581,7 +581,8 @@ void prep_box(RTLIL::Design *design, bool dff_mode) first = false; else ss << " "; - auto it = t.find(wire); + log_assert(GetSize(wire) == 1); + auto it = t.find(SigBit(wire,0)); if (it == t.end()) // Assume that no setup time means zero ss << 0; |