diff options
author | Clifford Wolf <clifford@clifford.at> | 2018-05-03 15:25:59 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2018-05-03 15:25:59 +0200 |
commit | a572b495387743a58111e7264917a497faa17ebf (patch) | |
tree | 103a3523b1868e31ec88d9b56ceb750f824bf487 /passes/techmap | |
parent | e060375f23d56b4e330a946d5a626f0163499618 (diff) | |
download | yosys-a572b495387743a58111e7264917a497faa17ebf.tar.gz yosys-a572b495387743a58111e7264917a497faa17ebf.tar.bz2 yosys-a572b495387743a58111e7264917a497faa17ebf.zip |
Replace -ignore_redef with -[no]overwrite
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/techmap')
-rw-r--r-- | passes/techmap/techmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 02d0d47e8..1908ae8b5 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -933,7 +933,7 @@ struct TechmapPass : public Pass { log(" -D <define>, -I <incdir>\n"); log(" this options are passed as-is to the Verilog frontend for loading the\n"); log(" map file. Note that the Verilog frontend is also called with the\n"); - log(" '-ignore_redef' option set.\n"); + log(" '-nooverwrite' option set.\n"); log("\n"); log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n"); log("match cells with a type that match the text value of this attribute. Otherwise\n"); @@ -1031,7 +1031,7 @@ struct TechmapPass : public Pass { simplemap_get_mappers(worker.simplemap_mappers); std::vector<std::string> map_files; - std::string verilog_frontend = "verilog -ignore_redef"; + std::string verilog_frontend = "verilog -nooverwrite"; int max_iter = -1; size_t argidx; |