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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-21 15:44:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | b65610fb628cfd38edcab3c64507477a58cbdd10 (patch) | |
| tree | 854e981f09c6868805ae603b3f50717ba3506550 /passes/techmap | |
| parent | ed7cb0b095e0eaf0ced643f7f828ea2c61b939b5 (diff) | |
| download | yosys-b65610fb628cfd38edcab3c64507477a58cbdd10.tar.gz yosys-b65610fb628cfd38edcab3c64507477a58cbdd10.tar.bz2 yosys-b65610fb628cfd38edcab3c64507477a58cbdd10.zip | |
abc9_ops: move assert
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 37d0528c1..b3f5b9919 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -263,9 +263,9 @@ void prep_bypass(RTLIL::Design *design) auto derived_type = inst_module->derive(design, cell->parameters); inst_module = design->module(derived_type); log_assert(inst_module); - log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */)); if (!inst_module->get_bool_attribute(ID::abc9_bypass)) continue; + log_assert(!inst_module->get_blackbox_attribute(true /* ignore_wb */)); // The idea is to create two techmap designs, one which maps: |