Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor

3 files changed, 55 insertions, 99 deletions

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index f44e3df06..a7e748ce7 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -101,6 +101,10 @@ struct Abc9Pass : public ScriptPass
 		log("        generate netlist using luts. Use the specified costs for luts with 1,\n");
 		log("        2, 3, .. inputs.\n");
 		log("\n");
+		log("    -dff\n");
+		log("        also pass $_ABC9_FF_ cells through to ABC. modules with many clock\n");
+		log("        domains are marked as such and automatically partitioned by ABC.\n");
+		log("\n");
 		log("    -nocleanup\n");
 		log("        when this option is used, the temporary files created by this pass\n");
 		log("        are not removed. this is useful for debugging.\n");
@@ -121,8 +125,8 @@ struct Abc9Pass : public ScriptPass
 		log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
 		log("ABC on logic snippets extracted from your design. You will not get any useful\n");
 		log("output when passing an ABC script that writes a file. Instead write your full\n");
-		log("design as an XAIGER file with write_xaiger and then load that into ABC externally\n");
-		log("if you want to use ABC to convert your design into another format.\n");
+		log("design as an XAIGER file with `write_xaiger' and then load that into ABC\n");
+		log("externally if you want to use ABC to convert your design into another format.\n");
 		log("\n");
 		log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
 		log("\n");
@@ -131,12 +135,13 @@ struct Abc9Pass : public ScriptPass
 	}
 
 	std::stringstream map_cmd;
-	bool cleanup;
+	bool dff_mode, cleanup;
 
 	void clear_flags() YS_OVERRIDE
 	{
 		map_cmd.str("");
 		map_cmd << "abc9_map";
+		dff_mode = false;
 		cleanup = true;
 	}
 
@@ -155,12 +160,16 @@ struct Abc9Pass : public ScriptPass
 				map_cmd << " " << arg << " " << args[++argidx];
 				continue;
 			}
-			if (arg == "-fast"
-					/*|| arg == "-nocleanup"*/ || arg == "-showtmp" || arg == "-markgroups"
-					|| arg == "-nomfs") {
+			if (arg == "-fast" || /* arg == "-dff" || */
+					/* arg == "-nocleanup" || */ arg == "-showtmp" || arg == "-markgroups" ||
+					arg == "-nomfs") {
 				map_cmd << " " << arg;
 				continue;
 			}
+			if (arg == "-dff") {
+				dff_mode = true;
+				continue;
+			}
 			if (arg == "-nocleanup") {
 				cleanup = false;
 				continue;
@@ -182,7 +191,8 @@ struct Abc9Pass : public ScriptPass
 		run("techmap @abc9_holes");
 		run("aigmap @abc9_holes");
 		run("select -list @abc9_holes");
-		run("abc9_ops -prep_dff");
+		if (dff_mode)
+			run("abc9_ops -prep_dff");
 		run("opt -purge @abc9_holes");
 		run("setattr -mod -set whitebox 1 @abc9_holes");
 
diff --git a/passes/techmap/abc9_map.cc b/passes/techmap/abc9_map.cc
index 9764d057c..9b56f04a8 100644
--- a/passes/techmap/abc9_map.cc
+++ b/passes/techmap/abc9_map.cc
@@ -199,7 +199,7 @@ struct abc9_output_filter
 void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
 		vector<int> lut_costs, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
 		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, std::string box_file, std::string lut_file,
-		std::string wire_delay, const dict<int,IdString> &box_lookup, bool nomfs, std::string tempdir_name
+		std::string wire_delay, bool nomfs, std::string tempdir_name
 )
 {
 	map_autoidx = autoidx++;
@@ -287,7 +287,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		log_assert(!design->module(ID($__abc9__)));
 		{
 			AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
-			reader.parse_xaiger(box_lookup);
+			reader.parse_xaiger();
 		}
 		ifs.close();
 		Pass::call_on_module(design, design->module(ID($__abc9__)), stringf("write_verilog -noexpr -norename -selected"));
@@ -339,7 +339,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		log_assert(!design->module(ID($__abc9__)));
 
 		AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
-		reader.parse_xaiger(box_lookup);
+		reader.parse_xaiger();
 		ifs.close();
 
 #if 0
@@ -899,66 +899,6 @@ struct Abc9MapPass : public Pass {
 		if (tempdir_name.empty())
 			log_cmd_error("abc9_map '-tempdir' option is mandatory.\n");
 
-		dict<int,IdString> box_lookup;
-		for (auto m : design->modules()) {
-			auto it = m->attributes.find(ID(abc9_box_id));
-			if (it == m->attributes.end())
-				continue;
-			if (m->name.begins_with("$paramod"))
-				continue;
-			auto id = it->second.as_int();
-			auto r = box_lookup.insert(std::make_pair(id, m->name));
-			if (!r.second)
-				log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
-						log_id(m), id, log_id(r.first->second));
-			log_assert(r.second);
-
-			RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
-			for (auto p : m->ports) {
-				auto w = m->wire(p);
-				log_assert(w);
-				if (w->attributes.count(ID(abc9_carry))) {
-					if (w->port_input) {
-						if (carry_in)
-							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
-						carry_in = w;
-					}
-					else if (w->port_output) {
-						if (carry_out)
-							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
-						carry_out = w;
-					}
-				}
-			}
-			if (carry_in || carry_out) {
-				if (carry_in && !carry_out)
-					log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
-				if (!carry_in && carry_out)
-					log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
-				// Make carry_in the last PI, and carry_out the last PO
-				//   since ABC requires it this way
-				auto &ports = m->ports;
-				for (auto it = ports.begin(); it != ports.end(); ) {
-					RTLIL::Wire* w = m->wire(*it);
-					log_assert(w);
-					if (w == carry_in || w == carry_out) {
-						it = ports.erase(it);
-						continue;
-					}
-					if (w->port_id > carry_in->port_id)
-						--w->port_id;
-					if (w->port_id > carry_out->port_id)
-						--w->port_id;
-					log_assert(w->port_input || w->port_output);
-					log_assert(ports[w->port_id-1] == w->name);
-					++it;
-				}
-				ports.push_back(carry_in->name);
-				carry_in->port_id = ports.size();
-				ports.push_back(carry_out->name);
-				carry_out->port_id = ports.size();
-			}
-		}
 
 		for (auto mod : design->selected_modules())
 		{
@@ -971,7 +911,7 @@ struct Abc9MapPass : public Pass {
 
 			abc9_module(design, mod, script_file, exe_file, lut_costs,
 					delay_target, lutin_shared, fast_mode, all_cells, show_tempdir,
-					box_file, lut_file, wire_delay, box_lookup, nomfs, tempdir_name);
+					box_file, lut_file, wire_delay, nomfs, tempdir_name);
 		}
 
 		log_pop();
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 019868adb..dcb8a8a78 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -108,33 +108,39 @@ void prep_dff(RTLIL::Module *module)
 	typedef SigSpec clkdomain_t;
 	dict<clkdomain_t, int> clk_to_mergeability;
 
-	for (auto cell : module->selected_cells()) {
-		auto inst_module = design->module(cell->type);
-		if (!inst_module || !inst_module->attributes.count("\\abc9_flop")
-				|| cell->get_bool_attribute("\\abc9_keep"))
-			continue;
+	//if (dff_mode)
+		for (auto cell : module->selected_cells()) {
+			if (cell->type != "$__ABC9_FF_")
+				continue;
 
-		Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
-		if (abc9_clock_wire == NULL)
-			log_error("'%s$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-		SigSpec abc9_clock = assign_map(abc9_clock_wire);
-
-		clkdomain_t key(abc9_clock);
-
-		auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
-		auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
-		log_assert(r2.second);
-
-		Wire *abc9_init_wire = module->wire(stringf("%s.$abc9_init", cell->name.c_str()));
-		if (abc9_init_wire == NULL)
-		    log_error("'%s.$abc9_init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-		log_assert(GetSize(abc9_init_wire) == 1);
-		SigSpec abc9_init = assign_map(abc9_init_wire);
-		if (!abc9_init.is_fully_const())
-		    log_error("'%s.$abc9_init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-		r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
-		log_assert(r2.second);
-	}
+			Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
+			if (abc9_clock_wire == NULL)
+				log_error("'%s.clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+			SigSpec abc9_clock = assign_map(abc9_clock_wire);
+
+			clkdomain_t key(abc9_clock);
+
+			auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
+			auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
+			log_assert(r2.second);
+
+			Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
+			if (abc9_init_wire == NULL)
+				log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+			log_assert(GetSize(abc9_init_wire) == 1);
+			SigSpec abc9_init = assign_map(abc9_init_wire);
+			if (!abc9_init.is_fully_const())
+				log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+			r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
+			log_assert(r2.second);
+		}
+	//else
+	//	for (auto cell : module->selected_cells()) {
+	//		auto inst_module = design->module(cell->type);
+	//		if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop"))
+	//			continue;
+	//		cell->set_bool_attribute("\\abc9_keep");
+	//	}
 
 	RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
 	if (holes_module) {
@@ -165,7 +171,7 @@ void prep_dff(RTLIL::Module *module)
 				// And drive the signal that was previously driven by "DFF.Q" (typically
 				//   used to implement clock-enable functionality) with the "<cell>.$abc9_currQ"
 				//   wire (which itself is driven an input port) we inserted above
-				Wire *currQ = holes_module->wire(stringf("%s.$abc9_currQ", driver.c_str()));
+				Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
 				log_assert(currQ);
 				holes_module->connect(Q, currQ);
 			}
@@ -412,7 +418,7 @@ void prep_holes(RTLIL::Module *module)
 				holes_wire->port_id = port_id++;
 				holes_module->ports.push_back(holes_wire->name);
 			}
-			Wire *w = holes_module->addWire(stringf("%s.$abc9_currQ", cell->name.c_str()));
+			Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
 			holes_module->connect(w, holes_wire);
 		}
 	}