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| author | Tim 'mithro' Ansell <me@mith.ro> | 2018-04-18 16:48:05 -0700 |
|---|---|---|
| committer | Tim 'mithro' Ansell <me@mith.ro> | 2018-04-18 16:55:12 -0700 |
| commit | d6bdefd2e93ad25fd63103d4b76a5573debc6d03 (patch) | |
| tree | 544397a34a4262465eb12b350469a9f63c0b19aa /passes/techmap | |
| parent | ca39e493ba78e7a4eaf3f0876321f892cce20f65 (diff) | |
| download | yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.tar.gz yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.tar.bz2 yosys-d6bdefd2e93ad25fd63103d4b76a5573debc6d03.zip | |
Improving vpr output support.
* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
Diffstat (limited to 'passes/techmap')
0 files changed, 0 insertions, 0 deletions