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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 07:49:02 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-15 07:49:02 -0700 |
| commit | d8a2aaa46379df7a07f4b776b7f9981b04999215 (patch) | |
| tree | b749ff51dec39f145cc25a1df262de7412f5c45a /passes/techmap | |
| parent | 704686774e28b9b602874264df2c0f96841be05e (diff) | |
| parent | 91f6cdfef6af69b7fe9203ee4d501ab6e6f1a830 (diff) | |
| download | yosys-d8a2aaa46379df7a07f4b776b7f9981b04999215.tar.gz yosys-d8a2aaa46379df7a07f4b776b7f9981b04999215.tar.bz2 yosys-d8a2aaa46379df7a07f4b776b7f9981b04999215.zip | |
Merge pull request #1297 from YosysHQ/eddie/fix_1284_again
extract_fa: Un-inverting AND with an inverted input also inverts input to X{,N}OR
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/extract_fa.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index b541ceb6b..8f195a90a 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -513,13 +513,13 @@ struct ExtractFaWorker } if (func2.at(key).count(xor2_func)) { - SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y; + SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(NEW_ID, Y) : Y; for (auto bit : func2.at(key).at(xor2_func)) assign_new_driver(bit, YY); } if (func2.at(key).count(xnor2_func)) { - SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y); + SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotGate(NEW_ID, Y); for (auto bit : func2.at(key).at(xnor2_func)) assign_new_driver(bit, YY); } |