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| author | Zachary Snow <zach@zachjs.com> | 2021-10-19 18:46:26 -0600 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-10-25 18:25:50 -0700 |
| commit | e833c6a418103feb30f0cc3e5c482da00ee9f820 (patch) | |
| tree | ef7d028ed17200f04558f3d2426f3db7ef6134cd /passes/techmap | |
| parent | bd16d01c0eed5c96a241e6ee9e56b8f7890319a1 (diff) | |
| download | yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.tar.gz yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.tar.bz2 yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.zip | |
verilog: use derived module info to elaborate cell connections
- Attempt to lookup a derived module if it potentially contains a port
connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
connections in a future change
Diffstat (limited to 'passes/techmap')
| -rw-r--r-- | passes/techmap/techmap.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index a69a6d460..5cd78fe28 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -377,10 +377,12 @@ struct TechmapWorker if (c->attributes.count(ID::src)) c->add_strpool_attribute(ID::src, extra_src_attrs); - if (techmap_replace_cell) + if (techmap_replace_cell) { for (auto attr : cell->attributes) if (!c->attributes.count(attr.first)) c->attributes[attr.first] = attr.second; + c->attributes.erase(ID::reprocess_after); + } } for (auto &it : tpl->connections()) { |