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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 09:51:32 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-02 09:51:32 -0700 |
| commit | 956ecd48f71417b514c194a833a49238049e00b0 (patch) | |
| tree | 468d55265c2549c86a8e7dfaf4ec0afffbd613bb /passes/tests/test_autotb.cc | |
| parent | 2d86563bb206748d6eef498eb27f7a004f20113d (diff) | |
| download | yosys-956ecd48f71417b514c194a833a49238049e00b0.tar.gz yosys-956ecd48f71417b514c194a833a49238049e00b0.tar.bz2 yosys-956ecd48f71417b514c194a833a49238049e00b0.zip | |
kernel: big fat patch to use more ID::*, otherwise ID(*)
Diffstat (limited to 'passes/tests/test_autotb.cc')
| -rw-r--r-- | passes/tests/test_autotb.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 2b6a86c25..1f071bd69 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -106,7 +106,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s RTLIL::Module *mod = it->second; - if (mod->get_bool_attribute("\\gentb_skip")) + if (mod->get_bool_attribute(ID::gentb_skip)) continue; int count_ports = 0; @@ -119,7 +119,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); } else if (wire->port_input) { count_ports++; - bool is_clksignal = wire->get_bool_attribute("\\gentb_clock"); + bool is_clksignal = wire->get_bool_attribute(ID::gentb_clock); for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); ++it3) for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); ++it4) { if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1) @@ -129,12 +129,12 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s if (c.wire == wire) is_clksignal = true; } - if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) { + if (is_clksignal && wire->attributes.count(ID::gentb_constant) == 0) { signal_clk[idy("sig", mod->name.str(), wire->name.str())] = wire->width; } else { signal_in[idy("sig", mod->name.str(), wire->name.str())] = wire->width; - if (wire->attributes.count("\\gentb_constant") != 0) - signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes["\\gentb_constant"].as_string(); + if (wire->attributes.count(ID::gentb_constant) != 0) + signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes[ID::gentb_constant].as_string(); } f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str()); } @@ -313,7 +313,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s f << stringf("\t// $dumpvars(0, testbench);\n"); f << stringf("\tfile = $fopen(`outfile);\n"); for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) - if (!it->second->get_bool_attribute("\\gentb_skip")) + if (!it->second->get_bool_attribute(ID::gentb_skip)) f << stringf("\t%s;\n", idy(it->first.str(), "test").c_str()); f << stringf("\t$fclose(file);\n"); f << stringf("\t$finish;\n"); |