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author | Clifford Wolf <clifford@clifford.at> | 2019-01-15 09:50:58 +0100 |
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committer | GitHub <noreply@github.com> | 2019-01-15 09:50:58 +0100 |
commit | 0994cfce7b15bbbea28a09e141a669c7228b6a89 (patch) | |
tree | 09ec8c096f9c779a3aae2280e61596dbc51a5a70 /passes/tests | |
parent | 2a2e0a4722ded7628b71f436b94a06aebd57bb62 (diff) | |
parent | e792bd56b77066ee048057e5efdb5d0f517b043a (diff) | |
download | yosys-0994cfce7b15bbbea28a09e141a669c7228b6a89.tar.gz yosys-0994cfce7b15bbbea28a09e141a669c7228b6a89.tar.bz2 yosys-0994cfce7b15bbbea28a09e141a669c7228b6a89.zip |
Merge pull request #787 from whitequark/flowmap_relax
flowmap: implement depth relaxation
Diffstat (limited to 'passes/tests')
-rw-r--r-- | passes/tests/flowmap/pack1.v | 11 | ||||
-rw-r--r-- | passes/tests/flowmap/pack1p.v | 11 | ||||
-rw-r--r-- | passes/tests/flowmap/pack2.v | 15 | ||||
-rw-r--r-- | passes/tests/flowmap/pack2p.v | 15 | ||||
-rw-r--r-- | passes/tests/flowmap/pack3.v | 15 | ||||
-rw-r--r-- | passes/tests/flowmap/pack3p.v | 15 |
6 files changed, 82 insertions, 0 deletions
diff --git a/passes/tests/flowmap/pack1.v b/passes/tests/flowmap/pack1.v new file mode 100644 index 000000000..9454edf3c --- /dev/null +++ b/passes/tests/flowmap/pack1.v @@ -0,0 +1,11 @@ +// Exact reproduction of Figure 3(a) from 10.1109/92.285741. +module top(...); + input a,b,c,d,e,f,g,h; + wire x = !(c|d); + wire y = !(e&f); + wire u = !(a&b); + wire v = !(x|y); + wire w = !(g&h); + output s = !(u|v); + output t = !(v|w); +endmodule diff --git a/passes/tests/flowmap/pack1p.v b/passes/tests/flowmap/pack1p.v new file mode 100644 index 000000000..fdb278833 --- /dev/null +++ b/passes/tests/flowmap/pack1p.v @@ -0,0 +1,11 @@ +// Like pack1.v, but results in a simpler network. +module top(...); + input a,b,c,d,e,f,g,h; + wire x = c|d; + wire y = e&f; + wire u = a&b; + wire v = x|y; + wire w = g&h; + output s = u|v; + output t = v|w; +endmodule diff --git a/passes/tests/flowmap/pack2.v b/passes/tests/flowmap/pack2.v new file mode 100644 index 000000000..445e4afb0 --- /dev/null +++ b/passes/tests/flowmap/pack2.v @@ -0,0 +1,15 @@ +// Exact reproduction of Figure 4(a) from 10.1109/92.285741. +module top(...); + (* $flowmap_level=1 *) input a; + (* $flowmap_level=1 *) input b; + (* $flowmap_level=2 *) input c; + (* $flowmap_level=1 *) input d; + (* $flowmap_level=3 *) input e; + (* $flowmap_level=1 *) input f; + wire u = !(a&b); + wire w = !(c|d); + wire v = !(u|w); + wire n0 = !(w&e); + wire n1 = !(n0|f); + output n2 = !(v&n1); +endmodule diff --git a/passes/tests/flowmap/pack2p.v b/passes/tests/flowmap/pack2p.v new file mode 100644 index 000000000..d4b41733d --- /dev/null +++ b/passes/tests/flowmap/pack2p.v @@ -0,0 +1,15 @@ +// Like pack2.v, but results in a simpler network. +module top(...); + (* $flowmap_level=1 *) input a; + (* $flowmap_level=1 *) input b; + (* $flowmap_level=2 *) input c; + (* $flowmap_level=1 *) input d; + (* $flowmap_level=3 *) input e; + (* $flowmap_level=1 *) input f; + wire u = a&b; + wire w = c|d; + wire v = u|w; + wire n0 = w&e; + wire n1 = n0|f; + output n2 = v&n1; +endmodule diff --git a/passes/tests/flowmap/pack3.v b/passes/tests/flowmap/pack3.v new file mode 100644 index 000000000..06147a1aa --- /dev/null +++ b/passes/tests/flowmap/pack3.v @@ -0,0 +1,15 @@ +// Exact reproduction of Figure 5(a) (bottom) from 10.1109/92.285741. +module top(...); + input a,b,c,d,e,f,g,h,i,j; + wire x = !(a&b); + wire y = !(c|d); + wire z = !(e|f); + wire n0 = !(g&h); + wire n1 = !(i|j); + wire w = !(x&y); + wire n2 = !(z&n0); + wire n3 = !(n0|n1); + wire n4 = !(n2|n3); + wire v = !(w|n5); + output u = !(w&v); +endmodule diff --git a/passes/tests/flowmap/pack3p.v b/passes/tests/flowmap/pack3p.v new file mode 100644 index 000000000..bc6ac1757 --- /dev/null +++ b/passes/tests/flowmap/pack3p.v @@ -0,0 +1,15 @@ +// Like pack2.v, but results in a simpler network. +module top(...); + input a,b,c,d,e,f,g,h,i,j; + wire x = a&b; + wire y = c|d; + wire z = e|f; + wire n0 = g&h; + wire n1 = i|j; + wire w = x&y; + wire n2 = z&n0; + wire n3 = n0|n1; + wire n4 = n2|n3; + wire v = w|n5; + output u = w&v; +endmodule |