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| author | clairexen <claire@symbioticeda.com> | 2020-05-29 16:37:23 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-29 16:37:23 +0200 |
| commit | 94c10353897c6b2b3f960bdd6647a5da9c1d9f2c (patch) | |
| tree | 695ca7d8b26c8c4268498c76e09c157d9846bde0 /passes/tests | |
| parent | af36afe722dc35b129351af592ef340e512e0292 (diff) | |
| parent | f88bef767263590c94e157d0989afa91db3ccdb0 (diff) | |
| download | yosys-94c10353897c6b2b3f960bdd6647a5da9c1d9f2c.tar.gz yosys-94c10353897c6b2b3f960bdd6647a5da9c1d9f2c.tar.bz2 yosys-94c10353897c6b2b3f960bdd6647a5da9c1d9f2c.zip | |
Merge pull request #1885 from Xiretza/mod-rem-cells
Fix modulo/remainder semantics
Diffstat (limited to 'passes/tests')
| -rw-r--r-- | passes/tests/test_cell.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index cdbe922b2..c6801007d 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -264,7 +264,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->setPort(ID::Y, wire); } - if (muxdiv && cell_type.in(ID($div), ID($mod))) { + if (muxdiv && cell_type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) { auto b_not_zero = module->ReduceBool(NEW_ID, cell->getPort(ID::B)); auto div_out = module->addWire(NEW_ID, GetSize(cell->getPort(ID::Y))); module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(div_out)), div_out, b_not_zero, cell->getPort(ID::Y)); @@ -839,6 +839,8 @@ struct TestCellPass : public Pass { cell_types[ID($mul)] = "ABSY"; cell_types[ID($div)] = "ABSY"; cell_types[ID($mod)] = "ABSY"; + cell_types[ID($divfloor)] = "ABSY"; + cell_types[ID($modfloor)] = "ABSY"; // cell_types[ID($pow)] = "ABsY"; cell_types[ID($logic_not)] = "ASY"; |