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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 21:45:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 22:31:04 -0700 |
| commit | 14e4aeece6adc0808ab1876f01752acb0833185a (patch) | |
| tree | ad1a92c62f9266402103a5d306f2c2daf51e6eb5 /passes | |
| parent | 8027ebf05b7538e501b4903cab9c2ce6a23610ff (diff) | |
| download | yosys-14e4aeece6adc0808ab1876f01752acb0833185a.tar.gz yosys-14e4aeece6adc0808ab1876f01752acb0833185a.tar.bz2 yosys-14e4aeece6adc0808ab1876f01752acb0833185a.zip | |
Fix comment
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 489887207..886e01c0f 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -614,7 +614,7 @@ struct XilinxDspPass : public Pass { xilinx_simd_pack(module, module->selected_cells()); // Match for all features ([ABDMP][12]?REG, pre-adder, - // (post-adder, pattern detector, etc.) except for CREG + // post-adder, pattern detector, etc.) except for CREG { xilinx_dsp_pm pm(module, module->selected_cells()); pm.run_xilinx_dsp_pack(xilinx_dsp_pack); |