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| author | Jannis Harder <me@jix.one> | 2023-02-13 12:26:06 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2023-02-13 12:26:06 +0100 |
| commit | 1698202ccc2f62d581673fd1320c3ab137f0261a (patch) | |
| tree | cebe60936fec53b518f37178e0b7e8df3c7ab7eb /passes | |
| parent | f3c4e93d2499dd96e331e49ad09540af9b9cd0bd (diff) | |
| download | yosys-1698202ccc2f62d581673fd1320c3ab137f0261a.tar.gz yosys-1698202ccc2f62d581673fd1320c3ab137f0261a.tar.bz2 yosys-1698202ccc2f62d581673fd1320c3ab137f0261a.zip | |
sim: For yw cosim, drive parent module's signals for input ports
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/sat/sim.cc | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index cfe31968d..7c209f516 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -139,6 +139,8 @@ struct SimInstance dict<SigBit, pool<Cell*>> upd_cells; dict<SigBit, pool<Wire*>> upd_outports; + dict<SigBit, SigBit> in_parent_drivers; + pool<SigBit> dirty_bits; pool<Cell*> dirty_cells; pool<IdString> dirty_memories; @@ -218,6 +220,12 @@ struct SimInstance dirty_bits.insert(sig[i]); } } + + if (wire->port_input && instance != nullptr && parent != nullptr) { + for (int i = 0; i < GetSize(sig); i++) { + in_parent_drivers.emplace(sig[i], parent->sigmap(instance->getPort(wire->name)[i])); + } + } } memories = Mem::get_all_memories(module); @@ -372,6 +380,22 @@ struct SimInstance return did_something; } + void set_state_parent_drivers(SigSpec sig, Const value) + { + sigmap.apply(sig); + + for (int i = 0; i < GetSize(sig); i++) { + auto sigbit = sig[i]; + auto sigval = value[i]; + + auto in_parent_driver = in_parent_drivers.find(sigbit); + if (in_parent_driver == in_parent_drivers.end()) + set_state(sigbit, sigval); + else + parent->set_state_parent_drivers(in_parent_driver->second, sigval); + } + } + void set_memory_state(IdString memid, Const addr, Const data) { set_memory_state(memid, addr.as_int(), data); @@ -1760,7 +1784,7 @@ struct SimWorker : SimShared log("yw: set %s to %s\n", signal.path.str().c_str(), log_const(value)); if (found_path.wire != nullptr) { - found_path.instance->set_state( + found_path.instance->set_state_parent_drivers( SigChunk(found_path.wire, signal.offset, signal.width), value); } else if (!found_path.memid.empty()) { |