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author | Clifford Wolf <clifford@clifford.at> | 2019-03-14 23:01:01 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-03-14 23:01:01 +0100 |
commit | 2a4263a75d0bbbc5b8f2de797b572d6f1d64818b (patch) | |
tree | 0d32025a044126c40f0a5bed673c6e86beaeae9d /passes | |
parent | 1b4fdbb0d881040220cdf1591f415cd2176481ad (diff) | |
download | yosys-2a4263a75d0bbbc5b8f2de797b572d6f1d64818b.tar.gz yosys-2a4263a75d0bbbc5b8f2de797b572d6f1d64818b.tar.bz2 yosys-2a4263a75d0bbbc5b8f2de797b572d6f1d64818b.zip |
Improve "mutate" wire coverage metric
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes')
-rw-r--r-- | passes/sat/mutate.cc | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index eac00948a..243a1b48a 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -289,6 +289,21 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena continue; SigMap sigmap(module); + dict<SigBit, int> bit_user_cnt; + + for (auto wire : module->wires()) { + if (wire->name[0] == '\\' && wire->attributes.count("\\src")) + sigmap.add(wire); + } + + for (auto cell : module->cells()) { + for (auto &conn : cell->connections()) { + if (cell->output(conn.first)) + continue; + for (auto bit : sigmap(conn.second)) + bit_user_cnt[bit]++; + } + } for (auto wire : module->selected_wires()) { @@ -331,7 +346,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena entry.src.insert(s); SigBit bit = sigmap(conn.second[i]); - if (bit.wire && bit.wire->name[0] == '\\') { + if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) { for (auto &s : bit.wire->get_strpool_attribute("\\src")) entry.src.insert(s); entry.wire = bit.wire->name; |