Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin

4 files changed, 148 insertions, 8 deletions

diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index cf9663d1d..c7edc30fb 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -5,6 +5,7 @@ OBJS += passes/cmds/design.o
 OBJS += passes/cmds/select.o
 OBJS += passes/cmds/show.o
 OBJS += passes/cmds/rename.o
+OBJS += passes/cmds/autoname.o
 OBJS += passes/cmds/connect.o
 OBJS += passes/cmds/scatter.o
 OBJS += passes/cmds/setundef.o
diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc
new file mode 100644
index 000000000..4614a8153
--- /dev/null
+++ b/passes/cmds/autoname.cc
@@ -0,0 +1,134 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+int autoname_worker(Module *module)
+{
+	dict<Cell*, pair<int, IdString>> proposed_cell_names;
+	dict<Wire*, pair<int, IdString>> proposed_wire_names;
+	dict<Wire*, int> wire_score;
+	int best_score = -1;
+
+	for (auto cell : module->selected_cells())
+	for (auto &conn : cell->connections())
+	for (auto bit : conn.second)
+		if (bit.wire != nullptr)
+			wire_score[bit.wire]++;
+
+	for (auto cell : module->selected_cells()) {
+		if (cell->name[0] == '$') {
+			for (auto &conn : cell->connections()) {
+				string suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first));
+				for (auto bit : conn.second)
+					if (bit.wire != nullptr && bit.wire->name[0] != '$') {
+						IdString new_name(bit.wire->name.str() + suffix);
+						int score = wire_score.at(bit.wire);
+						if (cell->output(conn.first)) score = 0;
+						score = 10000*score + new_name.size();
+						if (!proposed_cell_names.count(cell) || score < proposed_cell_names.at(cell).first) {
+							if (best_score < 0 || score < best_score)
+								best_score = score;
+							proposed_cell_names[cell] = make_pair(score, new_name);
+						}
+					}
+			}
+		} else {
+			for (auto &conn : cell->connections()) {
+				string suffix = stringf("_%s", log_id(conn.first));
+				for (auto bit : conn.second)
+					if (bit.wire != nullptr && bit.wire->name[0] == '$') {
+						IdString new_name(cell->name.str() + suffix);
+						int score = wire_score.at(bit.wire);
+						if (cell->output(conn.first)) score = 0;
+						score = 10000*score + new_name.size();
+						if (!proposed_wire_names.count(bit.wire) || score < proposed_wire_names.at(bit.wire).first) {
+							if (best_score < 0 || score < best_score)
+								best_score = score;
+							proposed_wire_names[bit.wire] = make_pair(score, new_name);
+						}
+					}
+			}
+		}
+	}
+
+	for (auto &it : proposed_cell_names) {
+		if (best_score*2 < it.second.first)
+			continue;
+		IdString n = module->uniquify(it.second.second);
+		log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
+		module->rename(it.first, n);
+	}
+
+	for (auto &it : proposed_wire_names) {
+		if (best_score*2 < it.second.first)
+			continue;
+		IdString n = module->uniquify(it.second.second);
+		log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
+		module->rename(it.first, n);
+	}
+
+	return proposed_cell_names.size() + proposed_wire_names.size();
+}
+
+struct AutonamePass : public Pass {
+	AutonamePass() : Pass("autoname", "automatically assign names to objects") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    autoname [selection]\n");
+		log("\n");
+		log("Assign auto-generated public names to objects with private names (the ones\n");
+		log("with $-prefix).\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-foo") {
+			// 	foo = true;
+			// 	continue;
+			// }
+			break;
+		}
+
+		log_header(design, "Executing AUTONAME pass.\n");
+
+		for (auto module : design->selected_modules())
+		{
+			int count = 0, iter = 0;
+			while (1) {
+				iter++;
+				int n = autoname_worker(module);
+				if (!n) break;
+				count += n;
+			}
+			if (count > 0)
+				log("Renamed %d objects in module %s (%d iterations).\n", count, log_id(module), iter);
+		}
+	}
+} AutonamePass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 5ae991b28..fb3896669 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -158,22 +158,25 @@ static void detect_fsm(RTLIL::Wire *wire)
 		std::set<sig2driver_entry_t> cellport_list;
 		sig2user.find(sig_q, cellport_list);
 
+		auto sig_q_bits = sig_q.to_sigbit_pool();
+
 		for (auto &cellport : cellport_list)
 		{
 			RTLIL::Cell *cell = cellport.first;
 			bool set_output = false, clr_output = false;
 
-			if (cell->type == "$ne")
+			if (cell->type.in("$ne", "$reduce_or", "$reduce_bool"))
 				set_output = true;
 
-			if (cell->type == "$eq")
+			if (cell->type.in("$eq", "$logic_not", "$reduce_and"))
 				clr_output = true;
 
-			if (!set_output && !clr_output) {
-				clr_output = true;
+			if (set_output || clr_output) {
 				for (auto &port_it : cell->connections())
-					if (port_it.first != "\\A" || port_it.first != "\\Y")
-						clr_output = false;
+					if (cell->input(port_it.first))
+						for (auto bit : assign_map(port_it.second))
+							if (bit.wire != nullptr && !sig_q_bits.count(bit))
+								goto next_cellport;
 			}
 
 			if (set_output || clr_output) {
@@ -184,6 +187,7 @@ static void detect_fsm(RTLIL::Wire *wire)
 						ce.set(sig, val);
 					}
 			}
+		next_cellport:;
 		}
 
 		SigSpec sig_y = sig_d, sig_undef;
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index 5807178dd..a2ad87f7d 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -394,7 +394,7 @@ struct FlowGraph
 
 	pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> edge_cut()
 	{
-		pool<RTLIL::SigBit> x, xi;
+		pool<RTLIL::SigBit> x = {source}, xi; // X and X̅ in the paper
 
 		NodePrime source_prime = {source, true};
 		pool<NodePrime> visited;
@@ -437,6 +437,7 @@ struct FlowGraph
 		for (auto collapsed_node : collapsed[sink])
 			xi.insert(collapsed_node);
 
+		log_assert(x[source] && !xi[source]);
 		log_assert(!x[sink] && xi[sink]);
 		return {x, xi};
 	}
@@ -1050,7 +1051,7 @@ struct FlowmapWorker
 
 				auto cut_inputs = cut_lut_at_gate(lut, lut_gate);
 				pool<RTLIL::SigBit> gate_inputs = cut_inputs.first, other_inputs = cut_inputs.second;
-				if (gate_inputs.empty() && (int)other_inputs.size() == order)
+				if (gate_inputs.empty() && (int)other_inputs.size() >= order)
 				{
 					if (debug_relax)
 						log("      Breaking would result in a (k+1)-LUT.\n");