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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 13:23:07 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-19 13:23:07 -0700 |
| commit | 3a87dc35242598b6951fb70d4302ede60c2a96b2 (patch) | |
| tree | 5cc7d61707ae1569f0170c7daaadabc89bd247f5 /passes | |
| parent | 31b0002e8c0e1b7a8ad054e02b1200c03461b581 (diff) | |
| download | yosys-3a87dc35242598b6951fb70d4302ede60c2a96b2.tar.gz yosys-3a87dc35242598b6951fb70d4302ede60c2a96b2.tar.bz2 yosys-3a87dc35242598b6951fb70d4302ede60c2a96b2.zip | |
Wrap A and B in sigmap
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/wreduce.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 23e14f7f5..294f0d57e 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -366,8 +366,8 @@ struct WreduceWorker } if (cell->type.in("$add", "$sub")) { - SigSpec A = cell->getPort("\\A"); - SigSpec B = cell->getPort("\\B"); + SigSpec A = mi.sigmap(cell->getPort("\\A")); + SigSpec B = mi.sigmap(cell->getPort("\\B")); bool sub = cell->type == "$sub"; int i; |