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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-26 10:27:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-26 10:27:30 -0700 |
| commit | 4c25d1a76fc006cac0d9e2038617f41ca90685c1 (patch) | |
| tree | d57c9ebcd6f7db64759b0fdee52f3b20d28fe894 /passes | |
| parent | c1a05f45577223c0585e93d728c8e04169c4598d (diff) | |
| download | yosys-4c25d1a76fc006cac0d9e2038617f41ca90685c1.tar.gz yosys-4c25d1a76fc006cac0d9e2038617f41ca90685c1.tar.bz2 yosys-4c25d1a76fc006cac0d9e2038617f41ca90685c1.zip | |
Pop the CO bit from O
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/ice40_dsp.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index c5655ad20..369cb211e 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -144,8 +144,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm) // SB_MAC16 Output Interface SigSpec O = st.sigO; - if (GetSize(O) == 33) + if (GetSize(O) == 33) { cell->setPort("\\CO", st.sigO[32]); + O.remove(32); + } else { log_assert(GetSize(O) <= 32); cell->setPort("\\CO", pm.module->addWire(NEW_ID)); |