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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-15 16:29:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 4cec21b93e62e9c43a0ab9618c0111ee65e520c1 (patch) | |
| tree | ebb686ef074dc53bd8f471d88f6af469bae340e7 /passes | |
| parent | 6c66030dfbcd93024f5f5bb602b9fcc58cb80a88 (diff) | |
| download | yosys-4cec21b93e62e9c43a0ab9618c0111ee65e520c1.tar.gz yosys-4cec21b93e62e9c43a0ab9618c0111ee65e520c1.tar.bz2 yosys-4cec21b93e62e9c43a0ab9618c0111ee65e520c1.zip | |
abc9_ops: -prep_dff_map to error if async flop found
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9_ops.cc | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index ee25866c3..62007c61e 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -181,7 +181,7 @@ void prep_dff_map(RTLIL::Design *design) for (auto cell : module->cells()) if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) { if (dff_cell) - log_error("More than one $_DFF_[NP]_ cell found in module '%s' marked (* abc9_flop *)\n", log_id(module)); + log_error("Module '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", log_id(module)); dff_cell = cell; // Block sequential synthesis on cells with (* init *) != 1'b0 @@ -207,10 +207,15 @@ void prep_dff_map(RTLIL::Design *design) goto continue_outer_loop; } } + else if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), + ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_), + ID($__DFFE_NN0), ID($__DFFE_NN1), ID($__DFFE_NP0), ID($__DFFE_NP1), + ID($__DFFE_PN0), ID($__DFFE_PN1), ID($__DFFE_PP0), ID($__DFFE_PP1))) + log_error("Module '%s' with (* abc9_flop *) contains an asynchronous $_DFFE?_[NP][NP][01]_? cell, which is not supported for sequential synthesis.\n", log_id(module)); else if (cell->type.in(ID($specify2), ID($specify3), ID($specrule))) specify_cells.emplace_back(cell); if (!dff_cell) - log_error("$_DFF_[NP]_ cell not found in module '%s' marked (* abc9_flop *)\n", log_id(module)); + log_error("Module '%s' with (* abc9_flop *) does not any contain $_DFF_[NP]_ cells.\n", log_id(module)); D = dff_cell->getPort(ID::D); @@ -229,9 +234,6 @@ void prep_dff_map(RTLIL::Design *design) D = w; } - if (GetSize(specify_cells) == 0) - log_error("Module '%s' marked (* abc9_flop *) contains no specify timing information.\n", log_id(module)); - // Rewrite $specify cells that end with $_DFF_[NP]_.Q // to $_DFF_[NP]_.D since it will be moved into // the submodule |