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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-06 07:29:21 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-12-06 07:29:21 +0100 |
| commit | 643f858acffcb40cce4686a5a039dc80c18b933d (patch) | |
| tree | 847980cba952fd340f3215bc34790a39215d9e39 /passes | |
| parent | 910d94b21214b78d841cfb32a724c4f0ea8b365d (diff) | |
| download | yosys-643f858acffcb40cce4686a5a039dc80c18b933d.tar.gz yosys-643f858acffcb40cce4686a5a039dc80c18b933d.tar.bz2 yosys-643f858acffcb40cce4686a5a039dc80c18b933d.zip | |
Bugfix in opt_expr handling of a<0 and a>=0
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/opt/opt_expr.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 0ba233c62..610edc5e9 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1406,7 +1406,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false) { if (sigConst.is_fully_zero()) { - RTLIL::SigSpec a_prime(RTLIL::State::S0, 1); + RTLIL::SigSpec a_prime(RTLIL::State::S0, GetSize(cell->getPort("\\Y"))); if (is_lt) { log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n", log_id(cell->type), log_id(cell)); |