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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 14:50:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-19 14:50:11 -0700 |
| commit | 64a72ed51e9d21cf5f30e3ff87856c808cf53a29 (patch) | |
| tree | e58db8c7a93861c0b500e922e8b1cbc4a9397d13 /passes | |
| parent | 517ca49963a8f186b9f7b54b63e576b4ffb5b847 (diff) | |
| download | yosys-64a72ed51e9d21cf5f30e3ff87856c808cf53a29.tar.gz yosys-64a72ed51e9d21cf5f30e3ff87856c808cf53a29.tar.bz2 yosys-64a72ed51e9d21cf5f30e3ff87856c808cf53a29.zip | |
Do not perform width-checks for DSP48E1 which is much more complicated
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index c6120695a..f0537670f 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -278,17 +278,6 @@ endmatch code sigC sigP if (postAdd) { sigC = port(postAdd, postAddAB == \A ? \B : \A); - - // TODO for DSP48E1, which will have sign extended inputs/outputs - //int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B)); - //int actual_mul_width = GetSize(sigP); - //int actual_acc_width = GetSize(sigC); - - //if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width)) - // reject; - //if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(postAdd, \A_SIGNED).as_bool())) - // reject; - sigP = port(postAdd, \Y); } endcode |