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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 10:29:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 10:29:16 -0700 |
| commit | 751e640c1db45f27a530738230b601417c2f2cdb (patch) | |
| tree | e394b686340915754168b556042077ded2fdda61 /passes | |
| parent | a3be25ab0d6040564ad9082db231478b21e021ac (diff) | |
| parent | 474fe9f47ae9c8a022d726a1b674853ca3236db0 (diff) | |
| download | yosys-751e640c1db45f27a530738230b601417c2f2cdb.tar.gz yosys-751e640c1db45f27a530738230b601417c2f2cdb.tar.bz2 yosys-751e640c1db45f27a530738230b601417c2f2cdb.zip | |
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index d90b421a8..99083c20a 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -22,7 +22,16 @@ // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification // http://www.eecs.berkeley.edu/~alanmi/abc/ +#if 0 +// Based on &flow3 - better QoR but more experimental +#define ABC_COMMAND_LUT "&st; &ps -l; "/*"&sweep -v;"*/" &scorr; " \ + "&st; &if {W}; &save; &st; &syn2; &if {W}; &save; &load; "\ + "&st; &if -g -K 6; &dch -f; &if {W}; &save; &load; "\ + "&st; &if -g -K 6; &synch2; &if {W}; &save; &load" +#else #define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; "*/"&retime; &dch -f; &ps -l; &if {W} -v; "/*"&mfs; "*/"&ps -l" +#endif + #define ABC_FAST_COMMAND_LUT "&st; &retime; &if {W}" |