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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-01 22:30:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 09:54:27 -0700 |
| commit | 789585a7445f8d63d9a251a9781434bc60d7f30c (patch) | |
| tree | cae538c30b90a9de12e05439540716725e6bc340 /passes | |
| parent | 8a8c1d7857d6ea475451e10fd14dbe6d117ca3de (diff) | |
| download | yosys-789585a7445f8d63d9a251a9781434bc60d7f30c.tar.gz yosys-789585a7445f8d63d9a251a9781434bc60d7f30c.tar.bz2 yosys-789585a7445f8d63d9a251a9781434bc60d7f30c.zip | |
Add TODO
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index df14f8f7e..f15aded84 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -736,6 +736,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } } + // TODO: Move this optimisation into parse_xaiger, so that we + // can get save on the "clean" call at the end of this function for (auto &it : bit_users) if (bit_drivers.count(it.first)) for (auto driver_cell : bit_drivers.at(it.first)) |