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| author | rafaeltp <rafaeltp@soe.ucsc.edu> | 2018-10-20 18:02:59 -0700 |
|---|---|---|
| committer | rafaeltp <rafaeltp@soe.ucsc.edu> | 2018-10-20 18:02:59 -0700 |
| commit | 7b964bfb83696ac66f31e560d8c0c475da2b5c10 (patch) | |
| tree | dca9e5ab0d1270884b319cfeeb6bc464ba50c12e /passes | |
| parent | ce069830c5f53643ea9e5bd26c20d13034a164d1 (diff) | |
| download | yosys-7b964bfb83696ac66f31e560d8c0c475da2b5c10.tar.gz yosys-7b964bfb83696ac66f31e560d8c0c475da2b5c10.tar.bz2 yosys-7b964bfb83696ac66f31e560d8c0c475da2b5c10.zip | |
cleaning up for PR
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/equiv/equiv_make.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index b4905f7c3..cfb4d4438 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -290,7 +290,7 @@ struct EquivMakeWorker init_bit2driven(); - pool<Cell*> visited_cells; + pool<Cell*> visited_cells; for (auto c : cells_list) for (auto &conn : c->connections()) if (!ct.cell_output(c->type, conn.first)) { @@ -418,7 +418,7 @@ struct EquivMakeWorker } } - bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigSpec source_bit, SigSpec target_bit) + bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit) { if (source_bit == target_bit) return true; |