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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 10:11:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 10:11:34 -0700 |
| commit | a5425a2f7e86f63ee4df84d15bf58fb9f006b465 (patch) | |
| tree | ca752a5606d63aa8b177de039e8ea8df62d52a47 /passes | |
| parent | d005568f2ea8825fdd47ae871f5bdeeaf7e27635 (diff) | |
| download | yosys-a5425a2f7e86f63ee4df84d15bf58fb9f006b465.tar.gz yosys-a5425a2f7e86f63ee4df84d15bf58fb9f006b465.tar.bz2 yosys-a5425a2f7e86f63ee4df84d15bf58fb9f006b465.zip | |
Remove extra semicolon
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/abc9.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index a6ec4a6fb..d90b421a8 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -395,7 +395,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n", // count_gates, GetSize(signal_list), count_input, count_output); - Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); + Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); std::string buffer; std::ifstream ifs; |