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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-24 12:56:05 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-24 12:56:05 +0100 |
| commit | aad195b88ce55d46fe741b217efc66b3aa259535 (patch) | |
| tree | 399a54e3670d36f305ff514c95d1e16cda2c89c2 /passes | |
| parent | 35f5aa300f4cdfc19293f0e5722159d7f0a212de (diff) | |
| download | yosys-aad195b88ce55d46fe741b217efc66b3aa259535.tar.gz yosys-aad195b88ce55d46fe741b217efc66b3aa259535.tar.bz2 yosys-aad195b88ce55d46fe741b217efc66b3aa259535.zip | |
Added "dfflibmap -prepare" help
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/techmap/dfflibmap.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 58f0c2542..cc6f97c7e 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -457,7 +457,7 @@ struct DfflibmapPass : public Pass { virtual void help() { log("\n"); - log(" dfflibmap -liberty <file> [selection]\n"); + log(" dfflibmap [-prepare] -liberty <file> [selection]\n"); log("\n"); log("Map internal flip-flop cells to the flip-flop cells in the technology\n"); log("library specified in the given liberty file.\n"); @@ -465,6 +465,10 @@ struct DfflibmapPass : public Pass { log("This pass may add inverters as needed. Therefore it is recommended to\n"); log("first run this pass and then map the logic paths to the target technology.\n"); log("\n"); + log("When called with -prepare, this command will convert the internal FF cells\n"); + log("to the internal cell types that best match the cells found in the given\n"); + log("liberty file.\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { |