Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp

3 files changed, 173 insertions, 5 deletions

diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 631a80aa5..cd357d72a 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -40,6 +40,7 @@ OBJS += passes/techmap/attrmap.o
 OBJS += passes/techmap/zinit.o
 OBJS += passes/techmap/dff2dffs.o
 OBJS += passes/techmap/flowmap.o
+OBJS += passes/techmap/extractinv.o
 endif
 
 GENFILES += passes/techmap/techmap.inc
diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc
new file mode 100644
index 000000000..dda71f12a
--- /dev/null
+++ b/passes/techmap/extractinv.cc
@@ -0,0 +1,123 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2019  Marcin Kościelnicki <mwk@0x04.net>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void split_portname_pair(std::string &port1, std::string &port2)
+{
+	size_t pos = port1.find_first_of(':');
+	if (pos != std::string::npos) {
+		port2 = port1.substr(pos+1);
+		port1 = port1.substr(0, pos);
+	}
+}
+
+struct ExtractinvPass : public Pass {
+	ExtractinvPass() : Pass("extractinv", "extract explicit inverter cells for invertible cell pins") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    extractinv [options] [selection]\n");
+		log("\n");
+		log("Searches the design for all cells with invertible pins controlled by a cell\n");
+		log("parameter (eg. IS_CLK_INVERTED on many Xilinx cells) and removes the parameter.\n");
+		log("If the parameter was set to 1, inserts an explicit inverter cell in front of\n");
+		log("the pin instead.  Normally used for output to ISE, which does not support the\n");
+		log("inversion parameters.\n");
+		log("\n");
+		log("To mark a cell port as invertible, use (* invertible_pin = \"param_name\" *)\n");
+		log("on the wire in the blackbox module.  The parameter value should have\n");
+		log("the same width as the port, and will be effectively XORed with it.\n");
+		log("\n");
+		log("    -inv <celltype> <portname_out>:<portname_in>\n");
+		log("        Specifies the cell type to use for the inverters and its port names.\n");
+		log("        This option is required.\n");
+		log("\n");
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing EXTRACTINV pass (extracting pin inverters).\n");
+
+		std::string inv_celltype, inv_portname, inv_portname2;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			std::string arg = args[argidx];
+			if (arg == "-inv" && argidx+2 < args.size()) {
+				inv_celltype = args[++argidx];
+				inv_portname = args[++argidx];
+				split_portname_pair(inv_portname, inv_portname2);
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (inv_celltype.empty())
+			log_error("The -inv option is required.\n");
+
+		for (auto module : design->selected_modules())
+		{
+			for (auto cell : module->selected_cells())
+			for (auto port : cell->connections()) {
+				auto cell_module = design->module(cell->type);
+				if (!cell_module)
+					continue;
+				auto cell_wire = cell_module->wire(port.first);
+				if (!cell_wire)
+					continue;
+				auto it = cell_wire->attributes.find("\\invertible_pin");
+				if (it == cell_wire->attributes.end())
+					continue;
+				IdString param_name = RTLIL::escape_id(it->second.decode_string());
+				auto it2 = cell->parameters.find(param_name);
+				// Inversion not used -- skip.
+				if (it2 == cell->parameters.end())
+					continue;
+				SigSpec sig = port.second;
+				if (it2->second.size() != sig.size())
+					log_error("The inversion parameter needs to be the same width as the port (%s.%s port %s parameter %s)", log_id(module->name), log_id(cell->type), log_id(port.first), log_id(param_name));
+				RTLIL::Const invmask = it2->second;
+				cell->parameters.erase(param_name);
+				if (invmask.is_fully_zero())
+					continue;
+				Wire *iwire = module->addWire(NEW_ID, sig.size());
+				for (int i = 0; i < sig.size(); i++)
+					if (invmask[i] == State::S1) {
+						RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
+						icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
+						icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
+						log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype.c_str(), log_id(module), log_id(cell->type), log_id(port.first), i);
+						sig[i] = SigBit(iwire, i);
+					}
+				cell->setPort(port.first, sig);
+			}
+		}
+	}
+} ExtractinvPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 51a65aea6..cf40b2f17 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -206,10 +206,27 @@ struct TechmapWorker
 
 		std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
 		dict<Wire*, IdString> temp_renamed_wires;
+		pool<SigBit> autopurge_tpl_bits;
 
-		for (auto &it : tpl->wires_) {
+		for (auto &it : tpl->wires_)
+		{
 			if (it.second->port_id > 0)
-				positional_ports[stringf("$%d", it.second->port_id)] = it.first;
+			{
+				IdString posportname = stringf("$%d", it.second->port_id);
+				positional_ports[posportname] = it.first;
+
+				if (!flatten_mode && it.second->get_bool_attribute(ID(techmap_autopurge)) &&
+						(!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) &&
+						(!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
+				{
+					if (sigmaps.count(tpl) == 0)
+						sigmaps[tpl].set(tpl);
+
+					for (auto bit : sigmaps.at(tpl)(it.second))
+						if (bit.wire != nullptr)
+							autopurge_tpl_bits.insert(it.second);
+				}
+			}
 			IdString w_name = it.second->name;
 			apply_prefix(cell->name, w_name);
 			RTLIL::Wire *w = module->wire(w_name);
@@ -232,6 +249,8 @@ struct TechmapWorker
 				w->port_input = false;
 				w->port_output = false;
 				w->port_id = 0;
+				if (!flatten_mode)
+					w->attributes.erase(ID(techmap_autopurge));
 				if (it.second->get_bool_attribute(ID(_techmap_special_)))
 					w->attributes.clear();
 				if (w->attributes.count(ID(src)))
@@ -362,11 +381,31 @@ struct TechmapWorker
 			if (!flatten_mode && c->type.begins_with("\\$"))
 				c->type = c->type.substr(1);
 
-			for (auto &it2 : c->connections_) {
-				apply_prefix(cell->name, it2.second, module);
-				port_signal_map.apply(it2.second);
+			vector<IdString> autopurge_ports;
+
+			for (auto &it2 : c->connections_)
+			{
+				bool autopurge = false;
+				if (!autopurge_tpl_bits.empty()) {
+					autopurge = GetSize(it2.second) != 0;
+					for (auto &bit : sigmaps.at(tpl)(it2.second))
+						if (!autopurge_tpl_bits.count(bit)) {
+							autopurge = false;
+							break;
+						}
+				}
+
+				if (autopurge) {
+					autopurge_ports.push_back(it2.first);
+				} else {
+					apply_prefix(cell->name, it2.second, module);
+					port_signal_map.apply(it2.second);
+				}
 			}
 
+			for (auto &it2 : autopurge_ports)
+				c->unsetPort(it2);
+
 			if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
 				IdString memid = c->getParam(ID(MEMID)).decode_string();
 				log_assert(memory_renames.count(memid) != 0);
@@ -1064,6 +1103,11 @@ struct TechmapPass : public Pass {
 		log("will create a wrapper for the cell and then run the command string that the\n");
 		log("attribute is set to on the wrapper module.\n");
 		log("\n");
+		log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n");
+		log("set, and that port is not connected in the instantiation that is mapped, then\n");
+		log("then a cell port connected only to such wires will be omitted in the mapped\n");
+		log("version of the circuit.\n");
+		log("\n");
 		log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
 		log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
 		log("the mapping module to the techmap command. At the moment the following special\n");